In known semiconductor devices, such as, for example, FinFET complementary metal-oxide-semiconductor (CMOS) devices, source drain (SD) regions are merged to reduce semiconductor resistance and decrease silicide contact resistance. However, the epitaxial merging and with it the needed overgrowth above the fins results in an increase of drain to gate capacitance because of an additional epitaxial region to gate capacitance component.
Accordingly, there is a need for a semiconductor device which can exhibit reduced semiconductor resistance and decreased silicide contact resistance without an increase in drain to gate capacitance.